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   <div id="projectname">CMSIS-Core (Cortex-A)
   &#160;<span id="projectnumber">Version 1.1.4</span>
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   <div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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<a href="#define-members">Macros</a>  </div>
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<div class="title">Peripheral Access</div>  </div>
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<p>Naming conventions and optional features for accessing peripherals.  
<a href="#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga286e3b913dbd236c7f48ea70c8821f4e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>(field, value)</td></tr>
<tr class="memdesc:ga286e3b913dbd236c7f48ea70c8821f4e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask and shift a bit field value for assigning the result to a peripheral register.  <a href="#ga286e3b913dbd236c7f48ea70c8821f4e">More...</a><br/></td></tr>
<tr class="separator:ga286e3b913dbd236c7f48ea70c8821f4e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga139b6e261c981f014f386927ca4a8444"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a>(field, value)</td></tr>
<tr class="memdesc:ga139b6e261c981f014f386927ca4a8444"><td class="mdescLeft">&#160;</td><td class="mdescRight">Extract from a peripheral register value the a bit field value.  <a href="#ga139b6e261c981f014f386927ca4a8444">More...</a><br/></td></tr>
<tr class="separator:ga139b6e261c981f014f386927ca4a8444"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p>The section below describes the naming conventions, requirements, and optional features for accessing device specific peripherals. Most of the rules also apply to the core peripherals. The <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> contains typically these definition and also includes the core specific header files.</p>
<p>The definitions for <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> can be generated using the <a href="../../SVD/html/index.html"><b>CMSIS-SVD</b></a> System View Description for Peripherals. Refer to <a href="../../SVD/html/svd_SVDConv_pg.html"><b>SVDConv.exe</b></a> for more information.</p>
<p>Each peripheral provides a data type definition with a name that is composed of:</p>
<ul>
<li>an optional prefix <b>&lt;<em>device abbreviation&gt;</em>_</b></li>
<li><b>&lt;<em>peripheral name</em>&gt;</b></li>
<li>postfix <b>_Type</b> or <b>_TypeDef</b> to identify a type definition.</li>
</ul>
<p>Examples:</p>
<ul>
<li><b>UART_TypeDef</b> for the peripheral <b>UART</b>.</li>
<li><b>IMX_UART_TypeDef</b> for the device family <b>IMX</b> and the peripheral <b>UART</b>.</li>
</ul>
<p>The data type definition uses standard C data types defined by the ANSI C header file &lt;stdint.h&gt;.</p>
<ul>
<li>IO Type Qualifiers are used to specify the access to peripheral variables. <table class="doxtable">
<tr>
<th align="left">IO Type Qualifier </th><th align="left">Type </th><th align="left">Description  </th></tr>
<tr>
<td align="left"><b>__IM</b> </td><td align="left">Struct member </td><td align="left">Defines 'read only' permissions </td></tr>
<tr>
<td align="left"><b>__OM</b> </td><td align="left">Struct member </td><td align="left">Defines 'write only' permissions </td></tr>
<tr>
<td align="left"><b>__IOM</b> </td><td align="left">Struct member </td><td align="left">Defines 'read / write' permissions </td></tr>
<tr>
<td align="left"><b>__I</b> </td><td align="left">Scalar variable </td><td align="left">Defines 'read only' permissions </td></tr>
<tr>
<td align="left"><b>__O</b> </td><td align="left">Scalar variable </td><td align="left">Defines 'write only' permissions </td></tr>
<tr>
<td align="left"><b>__IO</b> </td><td align="left">Scalar variable </td><td align="left">Defines 'read / write' permissions </td></tr>
</table>
The typedef <b>&lt;<em>device abbreviation</em>&gt;_UART_TypeDef</b> shown below defines the generic register layout for all UART channels in a device.</li>
</ul>
<div class="fragment"><div class="line"><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
<div class="line">        <a class="code" href="core__ca_8h.html#a7e25d9380f9ef903923964322e71f2f6">__O</a>  uint32_t UART_CR;            <span class="comment">// Offset: 0x0000 ( /W) Control Register </span></div>
<div class="line">        <a class="code" href="core__ca_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t UART_MR;            <span class="comment">// Offset: 0x0004 (R/W) Mode Register </span></div>
<div class="line">        <a class="code" href="core__ca_8h.html#a7e25d9380f9ef903923964322e71f2f6">__O</a>  uint32_t UART_IER;           <span class="comment">// Offset: 0x0008 ( /W) Interrupt Enable Register </span></div>
<div class="line">        <a class="code" href="core__ca_8h.html#a7e25d9380f9ef903923964322e71f2f6">__O</a>  uint32_t UART_IDR;           <span class="comment">// Offset: 0x000C ( /W) Interrupt Disable Register </span></div>
<div class="line">        <a class="code" href="core__ca_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t UART_IMR;           <span class="comment">// Offset: 0x0010 (R/ ) Interrupt Mask Register </span></div>
<div class="line">        <a class="code" href="core__ca_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t UART_SR;            <span class="comment">// Offset: 0x0014 (R/ ) Status Register </span></div>
<div class="line">        <a class="code" href="core__ca_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t UART_RHR;           <span class="comment">// Offset: 0x0018 (R/ ) Receive Holding Register </span></div>
<div class="line">        <a class="code" href="core__ca_8h.html#a7e25d9380f9ef903923964322e71f2f6">__O</a>  uint32_t UART_THR;           <span class="comment">// Offset: 0x001C ( /W) Transmit Holding Register </span></div>
<div class="line">        <a class="code" href="core__ca_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t UART_BRGR;          <span class="comment">// Offset: 0x0020 (R/W) Baud Rate Generator Register </span></div>
<div class="line">        <a class="code" href="core__ca_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t UART_CMPR;          <span class="comment">// Offset: 0x0024 (R/W) Comparison Register </span></div>
<div class="line">        <a class="code" href="core__ca_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t UART_RTOR;          <span class="comment">// Offset: 0x0028 (R/W) Receiver Time-out Register </span></div>
<div class="line">        <a class="code" href="core__ca_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t <a class="code" href="core__ca_8h.html#af7f66fda711fd46e157dbb6c1af88e04">RESERVED</a>[46];       <span class="comment">// Offset: 0x002C (R/ ) Reserved                     </span></div>
<div class="line">        <a class="code" href="core__ca_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t UART_WPMR;          <span class="comment">// Offset: 0x00E4 (R/W) Write Protection Mode Register </span></div>
<div class="line">} IMX_UART_TypeDef;</div>
</div><!-- fragment --><p>To access the registers of the UART defined above, pointers to this register structure are defined. If more instances of a peripheral exist, the variables have a postfix (digit or letter) that identifies the peripheral.</p>
<p><b>Example:</b> In this example, <b>IMX_UART2</b> and <b>IMX_UART3</b> are two pointers to UARTs defined with above register structure. <br/>
</p>
<div class="fragment"><div class="line"><span class="preprocessor">#define IMX_UART2   ((IMX_UART_TypeDef *) IMX_UART2_BASE)</span></div>
<div class="line"><span class="preprocessor">#define IMX_UART3   ((IMX_UART_TypeDef *) IMX_UART3_BASE)</span></div>
</div><!-- fragment --><dl class="section note"><dt>Note</dt><dd><ul>
<li>The prefix <b>IMX</b> is optional.</li>
</ul>
</dd></dl>
<p>The registers in the various UARTs can now be referred in the user code as shown below:<br/>
</p>
<div class="fragment"><div class="line">val = IMX_UART2-&gt;SR   <span class="comment">// is the Status Register of UART2.</span></div>
</div><!-- fragment --><hr/>
<h1><a class="anchor" id="core_cmsis_pal_min_reqs"></a>
Minimal Requirements</h1>
<p>To access the peripheral registers and related function in a device, the files <b><em>device.h</em></b> and <b><a class="el" href="core__ca_8h.html" title="CMSIS Cortex-A Core Peripheral Access Layer Header File. ">core_ca.h</a></b> define as a minimum: <br/>
<br/>
</p>
<ul>
<li>The <b>Register Layout Typedef</b> for each peripheral that defines all register names. RESERVED is used to introduce space into the structure for adjusting the addresses of the peripheral registers. <br/>
<br/>
<b>Example:</b> <div class="fragment"><div class="line"><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
<div class="line">{</div>
<div class="line">  <a class="code" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t C_CTLR;              <span class="comment">// Offset: 0x0000 (R/W) CPU Interface Control Register </span></div>
<div class="line">  <a class="code" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t C_PMR;               <span class="comment">// Offset: 0x0004 (R/W) Interrupt Priority Mask Register </span></div>
<div class="line">  <a class="code" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t C_BPR;               <span class="comment">// Offset: 0x0008 (R/W) Binary Point Register </span></div>
<div class="line">  <a class="code" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a>  uint32_t C_IAR;               <span class="comment">// Offset: 0x000C (R/ ) Interrupt Acknowledge Register </span></div>
<div class="line">  <a class="code" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a>  uint32_t C_EOIR;              <span class="comment">// Offset: 0x0010 ( /W) End Of Interrupt Register </span></div>
<div class="line">  <a class="code" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a>  uint32_t C_RPR;               <span class="comment">// Offset: 0x0014 (R/ ) Running Priority Register </span></div>
<div class="line">  <a class="code" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a>  uint32_t C_HPPIR;             <span class="comment">// Offset: 0x0018 (R/ ) Highest Priority Pending Interrupt Register </span></div>
<div class="line">  <a class="code" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t C_ABPR;              <span class="comment">// Offset: 0x001C (R/W) Aliased Binary Point Register </span></div>
<div class="line">  <a class="code" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a>  uint32_t C_AIAR;              <span class="comment">// Offset: 0x0020 (R/ ) Aliased Interrupt Acknowledge Register </span></div>
<div class="line">  <a class="code" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a>  uint32_t C_AEOIR;             <span class="comment">// Offset: 0x0024 ( /W) Aliased End Of Interrupt Register </span></div>
<div class="line">  <a class="code" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a>  uint32_t C_AHPPIR;            <span class="comment">// Offset: 0x0028 (R/ ) Aliased Highest Priority Pending Interrupt Register </span></div>
<div class="line">  <a class="code" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t C_STATUSR;           <span class="comment">// Offset: 0x002C (R/W) Error Reporting Status Register, optional </span></div>
<div class="line">  <a class="code" href="core__ca_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a>   uint32_t RESERVED1[40];       <span class="comment">// Offset: 0x0030 (R/ ) Reserved</span></div>
<div class="line">  <a class="code" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t C_APR[4];            <span class="comment">// Offset: 0x00D0 (R/W) Active Priority Register </span></div>
<div class="line">  <a class="code" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t C_NSAPR[4];          <span class="comment">// Offset: 0x00E0 (R/W) Non-secure Active Priority Register </span></div>
<div class="line">  <a class="code" href="core__ca_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a>   uint32_t RESERVED2[3];        <span class="comment">// Offset: 0x00F6 (R/ ) Reserved</span></div>
<div class="line">  <a class="code" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a>  uint32_t C_IIDR;              <span class="comment">// Offset: 0x00FC (R/ ) CPU Interface Identification Register </span></div>
<div class="line">  <a class="code" href="core__ca_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a>   uint32_t RESERVED3[960];      <span class="comment">// Offset: 0x0100 (R/ ) Reserved</span></div>
<div class="line">  <a class="code" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a>  uint32_t C_DIR;               <span class="comment">// Offset: 0x1000 ( /W) Deactivate Interrupt Register </span></div>
<div class="line">}  <a class="code" href="structGICInterface__Type.html">GICInterface_Type</a>;</div>
</div><!-- fragment --></li>
<li><b>Base Address</b> for each peripheral (in case of multiple peripherals that use the same <b>register layout typedef</b> multiple base addresses are defined). <br/>
<br/>
<b>Example:</b> <div class="fragment"><div class="line"><span class="preprocessor">#define GIC_INTERFACE_BASE (0xe8202000UL)   // GIC Interface Base Address     </span></div>
</div><!-- fragment --></li>
<li><b>Access Definitions</b> for each peripheral. In case of multiple peripherals that are using the same <b>register layout typedef</b>, multiple access definitions exist. <br/>
<br/>
<b>Example:</b> <div class="fragment"><div class="line"><span class="preprocessor">#define GICInterface   ((GICInterface_Type *) GIC_INTERFACE_BASE)   // GIC Interface Access Definition </span></div>
</div><!-- fragment --></li>
</ul>
<p>These definitions allow accessing peripheral registers with simple assignments.</p>
<ul>
<li><b>Example:</b> <br/>
<div class="fragment"><div class="line"><a class="code" href="group__GIC__functions.html#ga31a083dbdc5cb84178dbf184286180e3">GICInterface</a>-&gt;C_CTLR |= 1;   <span class="comment">// Enable Interface</span></div>
</div><!-- fragment --></li>
</ul>
<hr/>
<h1><a class="anchor" id="core_cmsis_pal_opts"></a>
Optional Features</h1>
<p>Optionally, the file <b><em>device</em>.h</b> may define:</p>
<ul>
<li><a class="el" href="group__peripheral__gr.html#core_cmsis_pal_bitfields">Register Bit Fields</a> and #define constants that simplify access to peripheral registers. These constants may define bit-positions or other specific patterns that are required for programming peripheral registers. The identifiers should start with <b>&lt;<em>device abbreviation</em>&gt;_</b> and <b>&lt;<em>peripheral name</em>&gt;_</b>. It is recommended to use CAPITAL letters for #define constants.</li>
<li>More complex functions (i.e. status query before a sending register is accessed). Again, these functions start with <b>&lt;<em>device abbreviation</em>&gt;_</b> and <b>&lt;<em>peripheral name</em>&gt;_</b>.</li>
</ul>
<hr/>
<h1><a class="anchor" id="core_cmsis_pal_bitfields"></a>
Register Bit Fields</h1>
<p>For Core Register, macros define the position and the mask value for a bit field.</p>
<p><b>Example:</b></p>
<p>Bit field definitions for register ACTLR in CP15.</p>
<div class="fragment"><div class="line"><span class="comment">// CP15 Register ACTLR</span></div>
<div class="line"><span class="preprocessor">#define ACTLR_DDI_Pos                  28U                       </span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define ACTLR_DDI_Msk                  (1UL &lt;&lt; ACTLR_DDI_Pos)    </span></div>
<div class="line"><span class="preprocessor"></span>                                       </div>
<div class="line"><span class="preprocessor">#define ACTLR_DDVM_Pos                 15U                       </span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define ACTLR_DDVM_Msk                 (1UL &lt;&lt; ACTLR_DDVM_Pos)   </span></div>
<div class="line"><span class="preprocessor"></span>                                       </div>
<div class="line"><span class="preprocessor">#define ACTLR_L1PCTL_Pos               13U                       </span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define ACTLR_L1PCTL_Msk               (3UL &lt;&lt; ACTLR_L1PCTL_Pos) </span></div>
<div class="line"><span class="preprocessor"></span>                                       </div>
<div class="line"><span class="preprocessor">#define ACTLR_L1RADIS_Pos              12U                       </span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define ACTLR_L1RADIS_Msk              (1UL &lt;&lt; ACTLR_L1RADIS_Pos)</span></div>
<div class="line"><span class="preprocessor"></span>                                       </div>
<div class="line"><span class="preprocessor">#define ACTLR_L2RADIS_Pos              11U                       </span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define ACTLR_L2RADIS_Msk              (1UL &lt;&lt; ACTLR_L2RADIS_Pos)</span></div>
<div class="line"><span class="preprocessor"></span>                                       </div>
<div class="line"><span class="preprocessor">#define ACTLR_DODMBS_Pos               10U                       </span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define ACTLR_DODMBS_Msk               (1UL &lt;&lt; ACTLR_DODMBS_Pos) </span></div>
<div class="line"><span class="preprocessor"></span>                                       </div>
<div class="line"><span class="preprocessor">#define ACTLR_SMP_Pos                  6U                        </span></div>
<div class="line"><span class="preprocessor">#define ACTLR_SMP_Msk                  (1UL &lt;&lt; ACTLR_SMP_Pos)     </span></div>
</div><!-- fragment --><p>The macros <b><a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e" title="Mask and shift a bit field value for assigning the result to a peripheral register. ">_VAL2FLD(field, value)</a></b> and <b><a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444" title="Extract from a peripheral register value the a bit field value. ">_FLD2VAL(field, value)</a></b> enable access to bit fields. </p>
<h2 class="groupheader">Macro Definition Documentation</h2>
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          <td class="memname">#define _FLD2VAL</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">field, </td>
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          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">value&#160;</td>
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          <td>)</td>
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<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">field</td><td>name of bit field. </td></tr>
    <tr><td class="paramname">value</td><td>value of the register. This parameter is interpreted as an uint32_t type.</td></tr>
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<p>The macro <a class="el" href="core__ca_8h.html#a139b6e261c981f014f386927ca4a8444">_FLD2VAL</a> uses the #define's <em>_Pos</em> and <em>_Msk</em> of the related bit field to extract the value of a bit field from a register.</p>
<p><b>Example:</b> </p>
<div class="fragment"><div class="line">i = <a class="code" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a>(ACTLR_SMP, ACTLR);</div>
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          <td class="memname">#define _VAL2FLD</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">field, </td>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">value&#160;</td>
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          <td>)</td>
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<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">field</td><td>name of bit field. </td></tr>
    <tr><td class="paramname">value</td><td>value for the bit field. This parameter is interpreted as an uint32_t type.</td></tr>
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  </dd>
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<p>The macro <a class="el" href="core__ca_8h.html#a286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a> uses the #define's <em>_Pos</em> and <em>_Msk</em> of the related bit field to shift bit-field values for assigning to a register.</p>
<p><b>Example:</b> </p>
<div class="fragment"><div class="line">ACTLR = <a class="code" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>(ACTLR_SMP, 0x1)</div>
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